library ieee;
use ieee.std_logic_1164.all;
entity code3_8_wy is
port (
a,b,c : in std_logic;
ena : in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic
);
end code3_8_wy;
architecture behavioral of code3_8_wy is
signal s :std_logic_vector(2 downto 0);
begin
s<=a&b&c;
process(s, ena)
begin
if ena = '1' then
case s is
when "000" =>
y0 <= '0'; y1 <= '1'; y2 <= '1'; y3 <= '1';