具有低电平异步复位功能，时钟clk上升沿触发的d触发器，请编写verilog程序

```verilog module d_flip_flop ( input wire clk, input wire rst, input wire d, output reg q ); always @ (posedge clk or posedge rst) begin if (rst) begin q <= 1'b0; end else begin q <= d; end end endmodule ``` [2024-12-18 23:17:28 | AI写代码神器 | 172点数解答]